1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly to a shift register incorporating a built-in level shifter that is capable of reducing power dissipation, wherein the level shifter includes thin film transistors having the same channel type.
2. Description of the Related Art
Generally, liquid crystal displays (LCDs) express images using electric fields to control the light transmittance characteristics of liquid crystal material. Accordingly, LCDs include a liquid crystal display panel having liquid crystal cells arranged in a matrix pattern and a driving circuit for driving the liquid crystal display panel.
Gate lines and data lines are arranged within the liquid crystal display panel to cross each other. Liquid crystal cells are arranged at crossings of the gate and data lines. Liquid crystal display panels include pixel electrodes and a common electrode that apply electric fields to each of the liquid crystal cells. Each pixel electrode is connected to a corresponding data line via source and drain terminals of a switching device such as a thin film transistor (TFT). A gate terminal of each of the thin film transistors is connected to a corresponding gate line.
Driving circuits include a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially drives the liquid crystal cells on the liquid crystal display panel by sequentially applying a scanning signal to the gate lines. When the gate lines are supplied with the scanning signal, the data driver applies a video signal to respective ones of the data lines. Pictures are displayed by applying an electric field between pixel electrodes of each of the liquid crystal cells in the LCD panel and the common electrode. Electric fields are applied in accordance with inputted video signals.
Depending upon whether a semiconductor layer in the TFT is amorphous silicon or polycrystalline silicon, TFTs used in LCDs are classified as being either amorphous silicon type TFTs or polycrystalline silicon type TFTs.
LCDs fabricated using amorphous silicon type TFTs have a relatively low pixel density because amorphous silicon has a relatively small charge mobility. Moreover, use of amorphous silicon type TFTs in LCDs is disadvantageous because fabricating gate and data drivers out of amorphous silicon tends to be expensive and the time required to fabricate LCDs using amorphous silicon type TFTs tends to be lengthy due to their need to be manufactured separately from, and mounted onto the liquid crystal display panel.
LCDs fabricated using polycrystalline silicon type TFTs have a relatively high pixel density because polycrystalline silicon has a relatively high charge mobility. Moreover, use of polycrystalline silicon type TFTs in LCDs is advantageous because they decrease the manufacturing cost of the gate and data drivers due to their ability to be formed with peripheral driving circuits buried and mounted in the liquid crystal display panel. Accordingly, an LCD employing polycrystalline silicon type TFTs will now be discussed in greater detail below.
FIG. 1 illustrates a schematic view of a related art LCD employing polycrystalline silicon type TFTs.
Referring to FIG. 1, the LCD includes a liquid crystal display panel 10 including a picture display area 12, a data shift register 14, a gate shift register 16, a sampling switching array 15, a printed circuit board PCB 20 supporting an integrated control chip 22 containing control circuitry and a data driver IC and a level shifter array 24 mounted on PCB 20, and a flexible printed circuit FPC film 18 connecting the liquid crystal display panel 10 to the PCB 20.
The picture display area 12 includes a plurality of liquid crystal cells (LCs) arranged in a matrix pattern and is capable of displaying a picture. Each of the liquid crystal cells LC includes a switching device such as a polycrystalline silicon type TFT arranged at a crossing of a gate line GL and a data line DL. As polycrystalline silicon TFTs have a charge mobility roughly a hundred times larger than that of amorphous silicon TFTs, polycrystalline silicon TFTs have a relatively fast response speed such that the liquid crystal cells LC are driven in a point sequence manner. The data lines DL receive video signals from the sampling switch array 15, driven by the data shift register 14. The gate lines GL receive scanning signals from the gate shift register 16.
Both the data shift register 14 and gate shift register 16 include a plurality of stages. The output terminals of stages in the data shift register 14 are connected to respective ones of sampling switches of the sampling switch array 15 while the output terminals of stages in the gate shift register 16 are connected to respective ones of the gate lines GL. FIG. 2 illustrates the plurality of stages included within the data and gate shift registers 14 and 16. Generally, the plurality of stages are connected in cascade and shift a source start pulse from the control chip 22. In the data shift register 14, the plurality of stages sequentially apply sampling signals to the sampling switches while, in the gate shift register 16, the plurality of stages sequentially apply scanning pulses to the gate lines GL.
Referring to FIG. 2, the stages ST1 to STn are connected to an input line of a start pulse SP in cascade in addition to three of four phase clock signal supplying lines (C1 to C4). The four phase clock signals C1 to C4 are sequentially applied in a phase-delayed manner by one clock (as shown in FIG. 3). Each of the stages ST1 to STn shifts the start pulse SP by one clock with the aid of three clock pulses from the first to fourth clock signals C1 to C4 and outputs the shifted start pulse SP. Signals SO1 to SOn are outputted from each of the stages ST1 to STn of the shift register, applied as sampling signals to the sampling switches, and applied as start pulses for each succeeding stage.
The sampling switch array 15 includes a plurality of sampling switches (not shown) driven by sampling signals outputted from the data shift register 14 a plurality of output terminals connected to corresponding ones of the data lines DL. The sampling switches sequentially sample video signals from the control chip 22 in response to the outputted sampling signal and apply the sampled video signals to the data lines DL.
Because polycrystalline silicon is used in fabricating the TFTs, components of the liquid crystal display panel 10 such as the picture display area 12, the data shift register 14, the sampling switching array 15, and the gate shift register 16 are formed concurrently. LCDs fabricated using TFTs having P and N channels (i.e., CMOS TFTs) beneficially have a driving voltage with a wide range and are used to form simple integrated circuits. The use of TFTs having P and N channels, however, is disadvantageous because manufacturing costs tend to be high and the device reliability is low because a number of processes are required. If the liquid crystal display panel 10 is fabricated using TFTs having only one type of channel (e.g., all P or all N-type channels), the cost of manufacturing the LCD can be reduced below what it costs to manufacture CMOS TFTs and a relatively high device reliability may be achieved because a reduced number of processes are required.
Referring back to FIG. 1, a control circuit (not shown) included within the control chip 22 sends externally inputted video data to the data driver IC (not shown) and provides driving control signals required by the data and gate shift register 14 and 16, respectively. The data driver IC (not shown) converts the video data outputted by the control circuit (not shown) into an analog video signal and applies the analog video signal to the sampling switch array 15 via the FPC film 18.
The level shifter array 24 increases swing widths of the driving control signals (e.g., clock signals, etc.) inputted from the control circuit (not shown) and applies the driving control signals having the increased swing widths to the data and gate shift registers 14 and 16, respectively. For example, the level shifter array 24 level-shifts a clock signal, outputted by the control circuit and having a swing voltage below 10V, such that the clock signal has a swing width of at least 10V (including a negative voltage) and outputs the level-shifted clock signal. The clock signal is level-shifted because a pulse having a swing width of at least 10V should be supplied to drive TFTs formed in the liquid crystal display panel 10.
If the liquid crystal display panel 10 includes PMOS thin film transistors, a driving pulse suitable for driving the PMOS thin film transistors included in the sampling switch array 15 and the picture display area 12 must have a swing width of at least 10V in a negative direction. In order to provide such a driving pulse, a pulse having a swing width of at least 10V in a negative direction must be applied to the gate and data shift registers 14 and 16 as a clock signal. Using the control chip 22, a clock signal having a swing width up to 10V may be easily produced, but a clock signal having a swing width greater than 10V or having a negative value is produced with difficulty. It is difficult to ensure device performance while generating a voltage having a swing width greater than 10V or having a negative voltage. Further, it is difficult to ensure device performance while manufacturing an IC on a single chip. Accordingly, in the LCD illustrated in FIG. 1, the level shifter array 24, used to level-shift a driving pulse of 10V into a driving pulse having a swing width of greater than 10V including a negative voltage, is provided as a separate chip mounted on the PCB 20. However, it is disadvantageous to mount external circuits to the PCB 20 because the PCB cannot be made compactly. Furthermore, a potentially excessive amount of power is consumed by the LCD since clock signals having both positive and negative voltages and having swing widths of at least 10V must be applied from the PCB 20 to the data shift register 14 and the gate shift register 16 of the liquid crystal display panel 10.